---
name: hardware-gallery-theory-to-circuit-scaffold-2026-05-15
description: "2026-05-15 STEP 1138 — Hardware Gallery (4 FPGA silicon + 8 Qiskit script metadata-only directory) + Theory-to-Circuit (SEED → D-FUMT₈ → Verilog + Qiskit auto-generation scaffold first step). 2 新 lens (#/hardware-gallery +"
metadata: 
  node_type: memory
  type: project
  originSessionId: afeeb7e7-fd4f-40a6-92be-a8a4a193cd0e
---

★★★★ 2026-05-15 STEP 1138 — Hardware Gallery + Theory-to-Circuit scaffold. 「新理論 → 即座に回路化」 gap への直接対応.

## Trigger

藤本さん指摘: 「Rei や Claude 先生が新たな理論等が生まれた時に直ぐに作ることが出来ないと意味が無い」 + 既存 OSS app + 独自 code が site のどこに反映されて今後追加可能か?

### Audit 結果 (実施直前)

- ✅ `#/three-layer-hybrid` (design diagram only)
- ✅ `#/design-tools` (25 tools reference matrix)
- ✅ `#/phi-catalog` (Paper 153 derived 14 entries)
- ✅ `#/security-lens` (D-FUMT₈ BOTH 教育)
- ❌ `hardware/phase-c/{02,03,04,05}/` Verilog + tcl + bitstream は site 反映 **なし**
- ❌ `scripts/quantum/dfumt8_*.py` 10 Qiskit script は site 反映 **なし**
- ❌ Tang silicon User Codes (0x000084BA / 0x00005C27 / 0x0000A5F4 / 0x00001D46) は paper 145 + memory のみ
- ❌ **「新理論 → 自動回路化 pipeline」 は未存在** (`grep theory-to-circuit / auto-circuit` で実装 0 件)

## 実施 (Hardware Gallery + Theory-to-Circuit 両方並行)

### Part A: Hardware Gallery lens

| File | 内容 |
|---|---|
| `data/hardware-gallery/registry.json` (1 file 新規) | 5/11 metadata-only 原則準拠. **9 entries** (4 FPGA silicon + 4 IBM Heron Qiskit + 1 dfumt8_qml_kernel). 各 entry に: step + date + board/device + User Code / Job ID + fidelity / pass rate + files paths (GitHub raw URL prefix) + paperReference + honestScope |
| `src/renderer/components/hardware-gallery/HardwareGalleryLens.tsx` (1 file 新規) | filter (all / fpga-silicon / quantum-script / design-tooling) + 累計 summary card + entry card (User Code / Job ID / fidelity / files dropdown / GitHub raw URL link / honestScope) + 「今後の追加 protocol」 panel |

**重要 design**: file 本体は repo / GitHub に留めて、 site は metadata only. GitHub raw URL fetch で第三者 contributor / chat Claude も file body にアクセス可能. scale limit ~3000 entries.

### Part B: Theory-to-Circuit auto-pipeline scaffold

| File | 内容 |
|---|---|
| `src/aios/theory-to-circuit/types.ts` | DFumt8Value + DFUMT8_VERILOG_LITERAL (3-bit literal mapping: TRUE=3'b001 / FALSE=3'b000 / BOTH=3'b010 / ...) + DFUMT8_QISKIT_UNITARY (TRUE→NOT / FALSE→NOP / BOTH→PHI / NEITHER→ADIABATIC / INFINITY→OMEGA / ZERO→PSI / FLOWING→XOR / SELF→RESET) + TheorySource / VerilogModule / QiskitScript / GeneratedCircuit types |
| `src/aios/theory-to-circuit/verilog-generator.ts` | 8 D-FUMT₈ value × Verilog template mapping. TRUE/FALSE = constant assign / BOTH = `a ^ b` XOR / NEITHER = `~(a \| b)` NOR / INFINITY = 24-bit free-running counter / ZERO = identity-with-reset / FLOWING = 3-bit LFSR x^3+x^2+1 / SELF = feedback shift register |
| `src/aios/theory-to-circuit/qiskit-generator.ts` | 8 D-FUMT₈ value × Qiskit Phase 1 native unitary mapping (Paper 145 v0.7 §B.8). TRUE=qc.x(0) / FALSE=qc.id(0) / BOTH=qc.h(0) / NEITHER=qc.ry(π/2) + qc.x / INFINITY=Bennett 6-qubit ancilla / ZERO=PSI ancilla / FLOWING=3-CNOT XOR chain / SELF=RESET 6-qubit 0-gate |
| `src/aios/theory-to-circuit/index.ts` | export + `generateCircuit(theory)` combined wrapper |
| `scripts/generate-theory-to-circuit-samples.ts` | 3 sample theory 一括生成 (Theory #196 peace TRUE / Wave 2 Songline INFINITY / Wave 4 Maya distributed BOTH) → `data/theory-to-circuit/generated/{theory-id}.v + .py + scaffold-status.json` |
| `src/renderer/components/theory-to-circuit/TheoryToCircuitLens.tsx` | sample selector (3 buttons with D-FUMT₈ color) + Verilog body display (monospace pre code) + Qiskit body display + GitHub raw URL link + 「Next step candidates」 panel |

### App.tsx + ReiLauncher + sync-index-html-bundle update

- App.tsx 2 import + 2 route (`#/hardware-gallery` + `#/theory-to-circuit`)
- ReiLauncher 2 menu entries (🔧 Hardware Gallery + 🧬 Theory-to-Circuit, category="理論探索")
- scripts/sync-index-html-bundle.ts DATA_DIRS +2 (hardware-gallery + theory-to-circuit)

## Test 結果

```
test/step1138-theory-to-circuit-test.ts
=== 8 test categories ===
  1. DFUMT8_VERILOG_LITERAL completeness
  2. DFUMT8_QISKIT_UNITARY completeness (expectedUnitary mapping)
  3. generateVerilog produces module for each D-FUMT₈ (8 values × 4 assertions = 32)
  4. generateQiskit produces script for each D-FUMT₈ (8 values × 4 assertions = 32)
  5. generateCircuit combines both with honestScope
  6. TRUE / FALSE / NEITHER / INFINITY specific bodies
  7. pre-generated samples exist (scaffold-status.json + 3 sample × {.v, .py})
  8. hardware-gallery registry exists + shape

結果: 105 passed, 0 failed
```

dev:build → CF Pages deploy verify:
- `dist-renderer/data/hardware-gallery/registry.json` ✅ mirror
- `dist-renderer/data/theory-to-circuit/generated/` ✅ 7 files (scaffold-status.json + 3 .v + 3 .py)
- bundle (`dist-renderer/assets/app-BwCHfM35.js`) に新 route 5 件参照 ✅

## Honest scope (本 STEP の限界)

### Hardware Gallery

- ✅ 「既存 artifacts を site から閲覧可能化」 達成 (metadata + GitHub raw URL fetch)
- ❌ Tang silicon の自動 program は不可 (manual Gowin EDA + USB Debugger workflow retain)
- ❌ IBM Heron real-hardware 自動 submit は不可 (manual Qiskit script + IBM Quantum Open Plan 600s/月 budget retain)

### Theory-to-Circuit scaffold

- ✅ 1 SEED_KERNEL theory → 1 Verilog module + 1 Qiskit script auto-generation **scaffold first step**
- ✅ 8 D-FUMT₈ value × Verilog + Qiskit template 8×8=64 mapping (Paper 145 v0.7 ALU lattice + Phase 1 native unitary 準拠)
- ❌ **NOT a full 1601-theory pipeline** (1 turn で実装可能な範囲は 3 sample のみ)
- ❌ Generated code は syntactically valid だが build verification (Gowin EDA / Qiskit Aer) は **manual step**
- ❌ Tang silicon への actual program は manual workflow retain
- ❌ SEED_KERNEL の各 theory に D-FUMT₈ value field 未付与 (sample では hardcoded). 全 1601 theory 一括処理は別 STEP

## Next step candidates (本 scaffold の延長)

1. **SeedTheory.dfumt8Value lookup**: 現状 sample TheorySource では hardcode. SEED_KERNEL の各 theory に dfumt8Value field 追加 + auto-extraction (axiom literal から推論) 実装. 1-2 hr
2. **Auto-build verification**: Verilator lint (Verilog syntax check) + Qiskit Aer simulate (functional verify) post-generation. 2-3 hr
3. **Tang silicon program automation**: build.tcl auto-generate + Gowin programmer CLI invocation. ★ ただし「**manual gate**」 retain (物理 silicon program は安全のため必ず藤本さん操作)
4. **IBM Heron submission template**: Open Plan 600s/月 budget aware queue submission. 1-2 hr
5. **Lens UI download**: Blob URL → save-as functionality. 30 min
6. **Full 1601-theory batch generation**: SEED_KERNEL 全 entry × 8 D-FUMT₈ → 1601 Verilog + 1601 Qiskit. ★ scale limit (3000 entry) 確認後. 1-2 日 substantial work

## 「新理論 → 即座に回路化」 gap への対応評価

| 質問 | 本 STEP 後の状態 |
|---|---|
| 既存 OSS app / 独自 code は site のどこに反映? | ✅ `#/hardware-gallery` (Tang silicon Verilog + IBM Heron Qiskit + design tooling registry, 9 entries) |
| 今後も追加可能? | ✅ `data/hardware-gallery/registry.json` の `entries[]` に追加 → dev:build → CF Pages auto-deploy (5/11 metadata-only 原則, scale ~3000 entries) |
| 新理論 → 即座に回路化? | ⚠ **scaffold first step 達成** (`#/theory-to-circuit` 3 sample auto-generation), **full pipeline は数週間 substantial work retain** |
| Verilog / Qiskit 物理 build は自動? | ❌ Gowin EDA + Tang silicon SRAM Program は manual (paper 145 v0.7 four-substrate workflow). IBM Heron submission は手動 Qiskit script + Open Plan budget |

## OUKC honest correction principle 適用

- **「自動 pipeline 完成」 narrative は overclaim** — scaffold first step に過ぎず, full 1601-theory pipeline は数週間以上の substantial work
- **Manual workflow retain は essential safety**: Tang silicon への physical program は藤本さん操作必須 (Phase C 安全 protocol per `feedback_phase_c_silicon_existence_claim.md`)
- **Generated code の build validation は別 step**: syntactically valid ≠ semantically correct. Gowin EDA + Qiskit Aer manual verify 必須

## Files

### 新規 (10 files)

- `data/hardware-gallery/registry.json`
- `data/theory-to-circuit/generated/scaffold-status.json`
- `data/theory-to-circuit/generated/theory-196-peace.{v,py}`
- `data/theory-to-circuit/generated/wave-2-songline-aboriginal.{v,py}`
- `data/theory-to-circuit/generated/wave-4-maya-distributed-zpqtmt.{v,py}`
- `src/aios/theory-to-circuit/{types.ts, verilog-generator.ts, qiskit-generator.ts, index.ts}`
- `src/renderer/components/hardware-gallery/HardwareGalleryLens.tsx`
- `src/renderer/components/theory-to-circuit/TheoryToCircuitLens.tsx`
- `scripts/generate-theory-to-circuit-samples.ts`
- `test/step1138-theory-to-circuit-test.ts` (105/105 PASS)

### Modified (3 files)

- `src/renderer/App.tsx` (+2 import +2 route)
- `src/renderer/components/launcher/ReiLauncher.tsx` (+2 menu entries)
- `scripts/sync-index-html-bundle.ts` (DATA_DIRS +2)
- `docs/SITE_COVERAGE_MAP.md` (STEP 1138 section + last update date)

## 連結 reference

- [[project_2026-05-14_pm_session_summary]] (STEP 1136 4 education lenses, design diagram / 25 tools matrix の前提)
- [[project_collatz_mathlib_contribution_prep_2026-05-15]] (本日先行 STEP)
- [[feedback_metadata_only_scale_design]] (5/11 永続原則, Hardware Gallery が直接適用)
- [[feedback_phase_c_silicon_existence_claim]] (Tang silicon manual workflow 安全 protocol)
- [[feedback_world_uniqueness_claim_controllable]] (「自動 pipeline」 overclaim 防止)
- Paper 145 v0.7 (4-substrate verification = manual workflow evidence, Tang Console + Tang Nano 9K + IBM Heron + Aer simulator)
- SITE_COVERAGE_MAP.md STEP 1138 section